About
Rachana H D is an Assistant Professor Trainee at RV University, Mysuru, with an academic background in Electronics and Communication Engineering and a strong interest in teaching, research, and technology. She holds a B.E. in Electronics and Communication Engineering from Malnad College of Engineering, Hassan, and pursued her M.Tech in Electronics at BMS College of Engineering, Bengaluru.
Her academic and professional interests span Digital Electronics, VLSI Design, Embedded Systems, Real-Time Operating Systems, Computer Architecture, and Hardware-Software Co-design. She has hands-on experience in VLSI design and verification using industry-standard tools such as Cadence Xcelium, Genus, Tempus, and Innovus, along with FPGA development using Xilinx Vivado.
Her project experience includes asynchronous FIFO design and verification, RTOS and QNX Neutrino implementation, and the development of an AI-based microcontroller recommendation chatbot integrating FastAPI and Sentence-BERT. She has also worked as an engineer in real-time data processing, developing data pipelines and API-based integrations using Python and SQL.
Her research interests include efficient digital hardware design, VLSI systems, hardware security, real-time systems, and emerging hardware-software technologies. Her research work on an optimized random number generator for power and area efficiency was presented at IEEE ICIICS 2025 and received the Best Paper Award.
As an educator, she is passionate about making technical concepts intuitive, practical, and engaging. She believes in creating learning environments that encourage curiosity, experimentation, problem-solving, and continuous learning.
Optimized Random Number Generator for Power and Area Efficiency
This work presents a hybrid random number generator designed to improve power and area efficiency while maintaining high-quality randomness. The architecture combines Xoroshiro, a 43-bit Linear Feedback Shift Register (LFSR), and a ring oscillator as an entropy source. The proposed design was implemented and evaluated on a Xilinx Zynq FPGA using Vivado. Its randomness was rigorously evaluated using the NIST SP 800-22 statistical test suite. The work demonstrates an efficient hardware-oriented approach to random number generation with potential applications in secure and resource-constrained digital systems. The research was presented at IEEE ICIICS 2025 and received the Best Paper Award.
Link: https://ieeexplore.ieee.org/document/11483551
VLSI and Digital Hardware Design – Design and optimization of efficient digital architectures with emphasis on power, area, performance, and reliability.
Hardware Security – Hardware-based approaches for secure systems, including efficient random number generation and entropy sources.
Digital Design Verification – RTL design and verification of reliable multi-clock-domain systems, including asynchronous FIFO architectures and metastability mitigation.
Embedded and Real-Time Systems – Real-time scheduling, multitasking, inter-process communication, and reliability mechanisms in embedded operating systems.
AI for Hardware Systems – Applying machine learning and semantic technologies to assist hardware selection and system-level decision making.
Research Interests
VLSI Design, Digital Design & Verification, Hardware Security, FPGA Systems, Embedded & Real-Time Systems, Hardware–Software Co-Design, AI for Hardware Systems
Best Paper Award – IEEE ICIICS 2025
Received the Best Paper Award for research on an optimized random number generator focusing on power and area efficiency
Student Vice Chair – IEEE, Malnad College of Engineering
Served as Student Vice Chair, organizing technical seminars, coordinating events, and supporting IEEE initiatives and funding activities.
Assistant Professor Trainee
School of Engineering
-
Mysuru